1. Field of the Invention
The present invention generally relates to a formal logic verification system and a formal logic verification method, and more particularly to a formal logic verification system and method in which details of a circuit represented by a register-transfer-level(RTL)-description are compared with details of the circuit represented by a gate-level netlist.
2. Description of the Background Art
During a process of designing a semiconductor integrated circuit, there is usually employed a method of representing a circuit configuration to be implemented in the form of RTL description and then logically compiling the RTL description into a gate-level netlist. The RTL description corresponds to representation of a circuit configuration, in the form of a description corresponding to a combinational logic gate for implementing a specific function and a description relating to transfer of data among registers such as flip-flops and latches. Further, the gate-level netlist corresponds to representation of a circuit configuration through use of logic formulas of gate elements.
FIG. 13 shows one example of an RTL description and a netlist, both of which represent the same circuit configuration. As shown in FIG. 13, in the RTL description, only one description [e.g., module SUB( . . . )] is provided for a plurality of functional blocks (SUB U1 to U3) having the same function. In the RTL description, this description is repeatedly used as a description for higher levels in hierarchy (i.e., functional blocks). In contrast, even when a plurality of functional blocks having the same function exist, descriptions for respective functional blocks (module SUB1 to SUB3) are provided.
To verify equivalence between the logic of an RTL description and the logic of a netlist through formal verification, or to verify logical equivalence between the RTL. description and the netlist through comparison between details of the RTL description and details of the netlist, there hash conventionally been employed a method of comparing a single functional block represented by the RTL description and each of the plurality of functional blocks represented by the netlist [indicated by reference numerals {circle around (1)}, {circle around (2)}, and {circle around (3)} shown in FIG. 13].
Since the RTL description and the netlist differ in structure, more time is required for comparing an RTL description relating to the functional block with a description relating to the same functional block in the form of a netlist. For this reason, conventional formal verification in which such a comparison is repeatedly carried out requires a long verification time.
The present invention has been conceived to solve the previously-mentioned problems, and a general object of the present invention is to provide a novel and useful formal logic verification system and method.
A more specific object of the present invention is to provide a formal logic verification system capable of shortening verification time by reducing frequencies of direct comparison between an RTL description and a netlist.
The above objects of the present invention are achieved by a formal logic verification system which verifies logical equivalence between an RTL description and a gate level netlist obtained through logical compilation of the RTL descriptions, through comparison between the RTL description and the gate level netlist. The system includes a RTL-to-netlist comparison unit which, when a plurality of identical functional blocks are included in a circuit, compares an RTL description relating to the functional blocks with one of a plurality of descriptions that relate to the functional blocks and are included in the netlist. The system also includes a netlist-to-netlist comparison unit which compares a plurality of descriptions relating to the functional blocks included in the netlist.
A second object of the present invention is to provide a formal logic verification method that enables shortening of verification time by reducing frequencies of direct comparison between an RTL description and a netlist.
The above objects of the present invention are achieved by a formal logic verification method for verifying logical equivalence between an RTL description and a gate level netlist obtained through logical compilation of the RTL descriptions through comparison between the RTL description and the gate level netlist. The method includes a step for comparing an RTL description relating to functional blocks having the same function with a description of the netlist. The comparison between the RTL description and the netlist is continued until a description logically matching the RTL description is found in a plurality of descriptions in the netlist. The method also includes a step for comparing a plurality of descriptions relating to the functional blocks included in the netlist with each other. The comparison between the netlist descriptions is performed while employing the description of the netlist that is acknowledged to logically match the RTL description as a reference description.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.